1. Field of the Invention
The present invention relates to a method and a circuit for writing data to a non-volatile semiconductor memory device. More particularly, the present invention relates to a method and a circuit for writing data to a non-volatile semiconductor memory device based on a write operation using secondary electrons.
2. Description of the Related Art
An ETOX (registered trademark of Intel; EPROM Thin Oxide) type non-volatile semiconductor memory device is the most widely used conventional non-volatile semiconductor memory device (a flash memory). Japanese Patent Publication for Opposition No. 6-82841 (Conventional Example 1) discloses a non-volatile semiconductor memory device of this type. Referring to FIG. 1, the structure of a cell of an ETOX type non-volatile semiconductor memory device will be described. The non-volatile semiconductor memory device cell includes a source 14a and a drain 14b which are formed on a substrate 10, with a channel layer 14c extending therebetween. A floating gate 16 is provided over the channel layer 14c via a tunnel oxide film 15. Moreover, a control gate 18 is provided over the floating gate 16 via an interlayer insulating film 17.
The principle of operation of an ETOX type non-volatile semiconductor memory device will now be described. Table 1 shows voltages to be applied respectively to the control gate 18, the source 14a, the drain 14b and the substrate 10 in a write mode, an erase mode, and a read mode.
In the write (programming) mode, a voltage of 10 V, for example, is applied to the control gate 18 of the memory cell to which data is to be written, a reference voltage of 0 V, for example, is applied to the source 14a thereof, and a voltage of 6 V, for example, is applied to the drain 14b. Then, a current of 500 xcexcA/cell flows through the channel layer 14c, thereby generating channel hot electrons (hereinafter, referred to as xe2x80x9cCHEsxe2x80x9d) in a portion of the drain 14b side of the memory cell where there is a high electric field. Basically, CHEs are high-energy electrons which are generated by a high electric field and which flow through the channel. When CHEs jump over the energy barrier of the tunnel oxide film so as to be injected into the floating gate 16, the threshold voltage of the memory cell increases. The drain of each memory cell to which no data is to be written is set to the reference voltage (e.g., 0 V). The memory cell to which data has been written as described above has a threshold voltage equal to or greater than 3.5 V as shown in FIG. 2 by the curve labelled xe2x80x9cProgrammed state (a)xe2x80x9d.
In the erase mode, a voltage of xe2x88x929 V, for example, is applied to the control gate 18 and a voltage of 6 V, for example, is applied to the source 14a, whereby electrons are withdrawn from the floating gate 16 on the source 14a side of the memory cell, thereby reducing the threshold voltage. In such a case, the memory cell has a threshold voltage as shown in FIG. 2 by the curve labelled xe2x80x9cErased state (b)xe2x80x9d. Thus, the threshold voltage of the memory cell whose data has been erased is less than or equal to 2.0 V.
For a memory cell to/from which data has been written/erased, a read operation can be performed by applying a voltage of 3 V to the control gate 18 and a voltage of 1 V to the drain 14b, while controlling the potential of the source 14a to be 0 V. Under such voltage conditions, if data stored in the memory cell is in the programmed state, the threshold voltage of the memory cell is equal to or greater than 3.5 V. Therefore, no current flows through the memory cell, whereby the data in the memory cell is determined to be xe2x80x9c0xe2x80x9d. If data stored in the memory cell is in the erased state, the threshold voltage of the memory cell is less than or equal to 2.0 V, and a current flows through the memory cell, whereby the data in the memory cell is determined to be xe2x80x9c1xe2x80x9d.
The write operation will now be described in greater detail with reference to FIG. 3. FIG. 3 illustrates the structure of a write circuit of Conventional Example 1.
The write circuit includes a memory cell array 300 including a plurality of memory cells N (M00, M01, . . . , M12) which are arranged in a matrix. Data can be electrically written to or erased from each of the memory cells M. The memory cells M are grouped into one or more blocks. In the example illustrated in FIG. 3, one block includes six memory cells. Each of the memory cells M00, M01, . . . , M12 in the memory cell array 300 has a field effect transistor including the floating gate 16 and the control gate 18. The sources 14a of the memory cells M in each block are coupled to a common source line 14A so that they are electrically connected to each other.
The write circuit of FIG. 3 further includes a row decoder 320 for supplying a voltage signal to the control gate 18 of each of the memory cells M via a word line WL, a program voltage application circuit 340 for applying a voltage signal to the drain 14b of the memory cell M via a bit line BL, a source voltage application circuit 360 for applying a voltage signal to the common source line 14A, and a high voltage charge pump 380 for supplying a voltage to these circuits (320, 340 and 360).
An exemplary write operation will now be described while describing the details of the write circuit of FIG. 3. Consider a case where data xe2x80x9c0xe2x80x9d (write enabled) and data xe2x80x9c1xe2x80x9d (write prohibited) are written to the memory cells M00 and M10, respectively, which are connected to the word line WL0, while no data is written to the memory cells M01, M11 and M02, M12, which are connected to the respective word lines WL1 and WL2.
When the write operation is initiated, the high voltage charge pump 380 increases a supply voltage V0 from a voltage source (not shown) so as to output a voltage V1 of 10 V, for example. The voltage V1 is decoded by the row decoder 320 into a voltage Vp of 10 V, for example, and output to the word line WL0. Whereas another voltage Vs of 0 V, for example, is output from the row decoder 320 to the word lines WL1 and WL2. Each of these voltages are applied to the control gate 18 of the memory cell M which is connected to the respective word line WL, thereby controlling whether or not to perform a write operation to the memory cell M.
The operation of applying a voltage to the drain 14b of the memory cell M via the bit line BL will be described. The voltage V1 from the high voltage charge pump 380 is regulated by a regulator circuit 1 to provide a stable voltage V1a (e.g., 6 V). Whether or not the voltage V1a is to be applied to each bit line BL is controlled by the MOS transistors (Tr01 and Tr02 or Tr11 and Tr12) which is connected to the bit line BL. The MOS transistors Tr01 and Tr11 are controlled by data which is externally provided via a node 1 and a node 2, respectively. Whereas the MOS transistors Tr02 and Tr12 together form a column switch 344 and are commonly controlled by an externally provided control signal Vc.
At the initiation of a write operation, a node 0 is brought to a xe2x80x9chighxe2x80x9d level (e.g., the level of the voltage V0) and the node 1 is brought to a xe2x80x9clowxe2x80x9d level (e.g., the reference voltage of 0 V) by the externally provided data. The xe2x80x9chighxe2x80x9d level at the node 0 is latched by a latch circuit 342a and then level-converted by a level shift circuit HV0 into a xe2x80x9chighxe2x80x9d level which corresponds to the level of the voltage Vp at a node H0. Thus, the MOS transistor Tr01 is turned ON. On the other hand, the xe2x80x9clowxe2x80x9d level at the node 1 is latched by a latch circuit 342b and then level-converted by a level shift circuit HV1 whose output is still at the xe2x80x9clowxe2x80x9d level (0 V). Thus, the MOS transistor Tr11 is OFF.
The externally provided control signal Vc at the xe2x80x9chighxe2x80x9d level (the level of the voltage V0) is provided to the column switch 344 which is provided in a subsequent stage following the MOS transistors Tr01 and Tr11. The control signal Vc is level-converted by a level shift circuit HV7 into the xe2x80x9chighxe2x80x9d level which corresponds to the level of the voltage Vp. This signal is input to all of the MOS transistors in the column switch 344, whereby the MOS transistors Tr02 and Tr12 are both turned ON.
Since the MOS transistors Tr01 and Tr02 are ON, the voltage V1a (e.g., 6 V) is applied to the memory cell M00 via the bit line BL0. On the other hand, the MOS transistor Tr11 is OFF, and thus the bit line BL1 is floating, whereby there is no voltage application to the memory cell M10.
The voltage application to the source 14a of the memory cell M is performed by the source voltage application circuit 360 as described above. The sources 14a of the memory cells M in one block are connected to the common source line 14A, and the voltage application to the common source line 14A is controlled by a MOS transistor Tr8. The MOS transistor Tr8 is turned ON by an externally provided control signal Vd at a xe2x80x9clowxe2x80x9d level, and the common source line 14A is brought to a level of the reference voltage Vs of 0 V, for example. A regulator circuit 2 is provided for applying a voltage Ve (e.g., 6 V) to the common source line 14A in an erase operation, and is irrelevant to the write operation. Thus, the regulator circuit 2 will not be further described below.
As described above, by applying the respective voltages for a write operation as shown in Table 1 to the memory cell M00, electrons are injected into the floating gate 16, whereby the threshold voltage of the memory cell M increases to be equal to or greater than 3.5 V. On the other hand, the memory cell M10, to which the voltage V1a is not applied, maintains its initial state where the threshold voltage is less than or equal to 2.0 V. Typically, a write operation involves a write operation for writing data to a memory cell and a verify operation for verifying the threshold voltage of the memory cell which has been changed by the write operation. The write and verify operations are performed alternately to each other so that the threshold voltage of the memory cell is controlled to be a predetermined value by verifying the threshold voltage.
Such a write operation has the following problems. Since the write operation is performed by generating CHEs, the amount of current consumed by the drain in a write operation for one memory cell is as large as 500 xcexcA. While the number of bits (the number of memory cells) to be written in parallel is two in the example described above, it is 16 or more for some commercially available LSIs (large scale integrated circuits). In such a case, the total amount of current to be consumed is as large as 8 mA, and thus the scale of the booster charge pump becomes very large. Recently, as portable terminal devices such as portable phones have become widespread, there have been attempts to reduce the supply voltage in order to reduce the current consumption. When the supply voltage is reduced, the area of the above-described charge pump circuit increases. For example, when the supply voltage is changed from 2.4 V to 1.8 V, the layout area of the charge pump circuit increases by a factor of about 4. Due to such circumstances, it is necessary to reduce the current consumption in the write operation in order to efficiently operate the non-volatile semiconductor memory device.
One solution to the above-described problem is a write method using secondary electrons. This method is disclosed in the Technical Digest of IEDM, p.279-282, 1997 (xe2x80x9cSecondary Electron Flashxe2x80x94a High Performance Low Power Flash Technology for 0.35 xcexcm and belowxe2x80x9d; Conventional Example 2). This write method will be described with reference to FIG. 4.
FIG. 4 is a cross-sectional view schematically illustrating the structure of a memory cell used in this write method. As compared to the memory cell shown in FIG. 1, the memory cell shown in FIG. 4 further includes an n-well (nxe2x88x92 type) 11 and a p-well (pxe2x88x92 type) 12. The source/drain regions (n+ type) 14a, 14b are formed on the p-well 12. The voltage V0 is applied to the n-well 11, and the p-well 12 and p-substrate 10 are electrically isolated from each other by the n-well 11. The structure as shown in FIG. 4 will be hereinafter referred to as a xe2x80x9ctriple-well structurexe2x80x9d. Elements in FIG. 4 that are functionally similar to those shown in FIG. 1 are provided with like reference numerals.
The write operation of a non-volatile semiconductor memory device having the memory cell of FIG. 4 is as follows. In the write operation, voltages of 5 V, 3.5 V and xe2x88x923 V are applied to the control gate 18, the drain 14b and the p-well 12, respectively. Thus, as shown in FIG. 4, a current (electrons) flows through the channel layer 14c, thereby generating electron-hole pairs through impact ionization in the vicinity of the drain 14b. The holes of the electron-hole pairs are accelerated and move toward the substrate 10. The holes generate further electron-hole pairs as they move across the depletion layer between the drain 14b (n+) and the p-well 12 (pxe2x88x92). Among the electron-hole pairs, those electrons having a high level of energy (referred to as xe2x80x9chot electronsxe2x80x9d or xe2x80x9csecondary electronsxe2x80x9d) are injected into the floating gate 16, thereby increasing the threshold voltage to be equal to or greater than 3.5 V.
According to Conventional Example 2 which employs this method, the write time is 7 xcexcs and the current consumption is less than or equal to 10 xcexcA. Thus, the current consumption is reduced to be 1/50 of the current consumption of the conventional example of FIG. 1, i.e., 500 xcexcA, thereby providing an improvement to the conventional example of FIG. 1.
The operations in the erase mode and the read mode are the same as those described above for Conventional Example 1. The applied voltages are summarized in Table 2.
The above-described write method according to Conventional Example 2 will now be described in greater detail with reference to FIG. 5. FIG. 5 illustrates the structure of a write circuit of a non-volatile semiconductor memory device having the memory cell of FIG. 4. As can be seen from a comparison to the write circuit (FIG. 3) using CHEs, the write circuit of FIG. 5 further includes a circuit (substrate bias control circuit 500) for controlling a backgate bias of the memory cell. Other than the substrate bias control circuit 500, the elements shown in FIG. 5 are similar, and thus denoted by like reference numerals, to those shown in FIG. 3.
For example, the substrate bias control circuit 500 is primarily composed of a negative voltage charge pump 610 and a convergence circuit 620, as shown in FIG. 6. The substrate bias control circuit 500 further includes a clock generation circuit 630 for controlling the output of the negative voltage charge pump 610, and a negative voltage level shifter NV and a MOS transistor 640 for controlling the output of the substrate bias control circuit 500. The negative voltage charge pump 610 includes P-channel MOS transistors, capacitors and inverter circuits, as shown in FIG. 6. The negative voltage level shifter NV has a structure as shown in FIG. 7.
The write operation by the write circuit of FIG. 5 having the substrate bias control circuit 500 will now be described. The write operation is basically the same as that of Conventional Example 1 described above except that a negative voltage is applied to the p-well 12 and that different voltage values are used. Again, consider a case where data xe2x80x9c0xe2x80x9d (write enabled) and data xe2x80x9c1xe2x80x9d (write prohibited) are written to the memory cells M00 and M10, respectively, which are connected to the word line WL0, while no data is written to the memory cells M01, M11 and M02, M12, which are connected to the respective word lines WL1 and WL2.
When the write operation is initiated, a control signal Vb transitions to the xe2x80x9chighxe2x80x9d level (the level of the voltage V0). In response to this, the clock generation circuit 630 starts its operation so as to output 2-phase clocks clk and clk bar, for example. Thus, the operation of the negative voltage charge pump 610 is initiated so as to output a negative voltage as the output of the negative voltage charge pump 610. A voltage detection is performed by resistance division using a voltage Vc and a negative voltage, and when the negative voltage value becomes greater than a Ref voltage value, a reset signal Vr is input to the clock generation circuit 630 from the convergence circuit 620. In response to the reset signal Vr input thereto, the clock generation circuit 630 stops clocking, thereby terminating the operation of the negative voltage charge pump 610. Thus, the negative voltage charge pump 610 is repeatedly switched between an operating state and a non-operating state by the reset signal Vr, whereby the negative voltage takes a value of about xe2x88x923 V as necessary.
The negative voltage level shifter NV converts the signal level of a control signal Vb. In particular, an input at the xe2x80x9chighxe2x80x9d level (the level of the voltage V0) is converted to a negative voltage (e.g., xe2x88x923 V), and an input at the xe2x80x9clowxe2x80x9d level (the level of the reference voltage Vs) is converted to the level of the voltage V0. Thus, during a write operation (when the control signal Vb is at the xe2x80x9chighxe2x80x9d level), the MOS transistor 640 is turned OFF, whereby an output voltage Vf, which is a negative voltage (xe2x88x923 V), is output to the output terminal t of the substrate bias control circuit 500. The output voltage Vf is applied to the p-well 12 of the memory cell as a backgate bias of the memory cell.
On the other hand, the charge pump 380 increases the supply voltage V0 from the voltage source (not shown) so as to output the voltage V1 of 5 V, for example. The voltage V1 is decoded by the row decoder 320 into the voltage Vp of 10 V, for example, and output to the word line WL0. Whereas, the voltage Vs of 0 V, for example, is output from the row decoder 320 to the non-selected word lines WL1 and WL2. Each of these voltages are applied to the control gate 18 of the memory cell M which is connected to the respective word line WL, thereby controlling whether or not to perform a write operation to the memory cell M.
The operation of applying a voltage to the drain 14b of the memory cell M via the bit line BL will be described. The voltage V1 from the high voltage charge pump 380 is regulated by the regulator circuit 1 to provide a stable voltage V1a (e.g., 3.5 V). Whether or not the voltage V1a is to be applied to each bit line BL is controlled by the MOS transistors (Tr01 and Tr02 or Tr11 and Tr12) which is connected to the bit line BL. The MOS transistors Tr01 and Tr11 are controlled by data which is externally provided via the node 0 and the node 1, respectively. Whereas the MOS transistors Tr02 and Tr12 together form the column switch 344 and are commonly controlled by the externally provided control signal Vc.
At the initiation of a write operation, data is transferred to the node 0 and the node 1, whereby the node 0 and the node 1 are brought to the xe2x80x9chighxe2x80x9d level and the xe2x80x9clowxe2x80x9d level, respectively. The xe2x80x9chighxe2x80x9d level at the node 0 is latched by the latch circuit 342a and then level-converted by the level shift circuit HV0 into the xe2x80x9chighxe2x80x9d level which corresponds to the level of the voltage Vp at the node H0. Thus, the MOS transistor Tr01 is turned ON. On the other hand, the xe2x80x9clowxe2x80x9d level at the node 1 is latched by the latch circuit 342b and then level-converted by the level shift circuit HV1 whose output is still at the xe2x80x9clowxe2x80x9d level (0 V). Thus, the MOS transistor Tr11 is OFF.
The externally provided control signal Vc at the xe2x80x9chighxe2x80x9d level is provided to the column switch 344 which is provided in a subsequent stage following the MOS transistors Tr01 and Tr11. The control signal Vc is level-converted by the level shift circuit HV7 into the xe2x80x9chighxe2x80x9d level which corresponds to the level of the voltage Vp. This signal is input to all of the MOS transistors in the column switch 344, whereby the MOS transistors Tr02 and Tr12 are both turned ON. Each of the level shift circuits HV have a structure as shown in FIG. 8.
Since the MOS transistors Tr01 and Tr02 are ON, the voltage V1a (3.5 V) is applied to the memory cell M00 via the bit line BL0. On the other hand, the MOS transistor Tr11 is OFF, and thus the bit line BL1 is floating, whereby there is no voltage application to the memory cell M10.
The common source line 14A for the memory cells M is at the reference voltage Vs of 0 V, for example, as described above with reference to FIG. 3.
As described above, by applying the respective voltages for a write operation as shown in Table 2 to the memory cell M00, electrons are injected into the floating gate 16, whereby the threshold voltage of the memory cell M increases to be equal to or greater than 3.5 V. On the other hand, the memory cell M10, to which the voltage V1a is not applied, maintains its initial state where the threshold voltage is less than or equal to 2.0 V.
In a program verify operation for verifying the threshold voltage of a memory cell after data has been written thereto, first, the voltage Vb input to the negative voltage level shifter NV becomes xe2x80x9clowxe2x80x9d, whereby a voltage which has been reduced to the reference voltage Vs through a discharge is output from the negative voltage level shifter NV as the output voltage Vf. Then, the potential of the word line WL0 is brought to 3.5 V to perform a read operation as a verify operation. When it is determined that the threshold voltage of the memory cell M00 is equal to or greater than 3.5 V, the write operation is completed. When the threshold voltage of the memory cell M00 is less than 3.5 V, a write operation is repeated by again applying a write signal. Thus, the write and verify operations are performed alternately to each other so that the threshold voltage of the memory cell is controlled to be a predetermined value (equal to or greater than 3.5 V) by verifying the threshold voltage.
However, Conventional Example 2 employing the write operation using secondary electrons has the following problems: (1) in a write operation, it is necessary to control the potential of the p-well 12 to be a negative value, and it takes a long time to charge the p-well 12 so that the potential thereof is negative, thereby increasing the write time; and (2) since the p-well 12 is charged to a negative potential, a negative voltage charge pump circuit is required which increases the layout area of the device.
The first problem (1) is further discussed below. For example, a 16 M non-volatile semiconductor memory device has a p-well whose capacitance is about 10000 pf. Therefore, when the p-well is to be charged to xe2x88x923 V by using a negative voltage charge pump whose charging capability is 1 mA, the amount of time t required for charging the p-well to xe2x88x923 V is obtained as follows:
t=10000pfxc3x973V/1 mA=30xcexcs
As can be seen from this calculation, at least 30 xcexcs is required for charging the p-well to xe2x88x923 V. Since the p-well is of a pxe2x88x92 type and thus has a high resistance, it actually requires more than 30 xcexcs until the voltage in the central portion of the well is completely stabilized. Moreover, the verify operation is performed by discharging the p-well, which takes about 10 xcexcs. Thus, the amount of time required for the entire write operation is 40 xcexcs, which only accounts for the amount of time required for charging and discharging the p-well. The amount of time which is actually required for a write operation is about 13 xcexcs excluding the amount of time for charging and discharging the p-well. The particulars of the time period are as follows: pulse application time: 7 xcexcs, word line set-up time: 100 ns, bit line set-up time: 100 ns, charge pump start-up time: 2 xcexcs, discharge time for the charge pump voltage, etc.: 1 xcexcs, verify time: 2 xcexcs, and circuit overhead: 1 xcexcs. The word line set-up time can be ignored in the calculation because the word line set-up time can overlap the charge pump set-up time. Therefore, the total amount of time required for the entire write operation is about 13 xcexcs (7 xcexcs+2 xcexcs+1 xcexcs+2 xcexcs+1 xcexcs+100 ns). As can be seen, the well voltage set-up time is much longer than these amounts of time, thereby increasing the write time and preventing one from achieving a high-speed write operation.
The second problem (2) is discussed below. A negative voltage charge pump needs to have a charging capability of about 1 mA in view of the well capacitance, as described above. However, the efficiency of a negative voltage charge pump is typically as low as about 10%. Therefore, the layout area for the negative voltage charge pump is increased (e.g., about 1% of the chip area), thereby increasing the chip area of the device.
According to one aspect of this invention, there is provided a method for writing data to a non-volatile semiconductor memory device including a plurality of memory cells which are arranged in a matrix in which data can be electrically written to or erased from the memory cells, the plurality of memory cells being grouped into one or more blocks, the memory cells in each block being provided on a same semiconductor base, each of the memory cells having a field effect transistor including a drain, a source, a floating gate and a control gate, the sources of the memory cells in each block being electrically connected to each other. The method performs a write operation to at least one of the plurality of memory cells in which the method includes the steps of: applying a first voltage to the control gate; applying a second voltage to the drain; applying a third voltage to the source; and applying a fourth voltage to the semiconductor base, the fourth voltage having a zero or positive value which is lower than the third voltage, wherein the first voltage, the second voltage, the third voltage and the fourth voltage are different from one other.
In one embodiment of the invention, the write operation is performed by secondary electrons being generated on the drain side of the non-volatile semiconductor memory device and injected into the floating gate. The first voltage, the second voltage and the third voltage are positive voltages. The first voltage is higher than the second voltage. The second voltage is higher than the third voltage.
In one embodiment of the invention, the third voltage is equal to a supply voltage output from a voltage source provided for supplying a voltage to the memory cells.
In one embodiment of the invention, the third voltage is higher than a supply voltage output from a voltage source provided for supplying a voltage to the memory cells.
In one embodiment of the invention, the third voltage is obtained by generating a fifth voltage higher than the supply voltage from the voltage source by using a charge pump circuit and by regulating the fifth voltage so as to decrease a level of the fifth voltage.
According to another aspect of this invention, there is provided a circuit for writing data to a non-volatile semiconductor memory device including a plurality of memory cells which are arranged in a matrix in which data can be electrically written to or erased from the memory cells, the plurality of memory cells being grouped into one or more blocks, the memory cells in each block being provided on a same semiconductor base, each of the memory cells having a field effect transistor including a drain, a source, a floating gate and a control gate, the sources of the memory cells in each block being electrically connected to each other. A voltage path is provided between the source and the semiconductor base, the voltage path including an element capable of causing a voltage drop.
In one embodiment of the invention, a plurality of the voltage paths are provided in parallel, the number of the voltage paths being equal to the number of columns of the memory cells matrix.
In one embodiment of the invention, the element capable of causing a voltage drop is a resistive element.
In one embodiment of the invention, the voltage path is in an ON state only during a write operation, and a voltage is supplied to the source from an external circuit during a period of time other than the write operation.
In one embodiment of the invention, the circuit further includes a control circuit for ensuring that during a write operation, in each block, a number of columns of the memory cells matrix to which data is simultaneously written and a number of voltage paths which are simultaneously in an ON state.
In one embodiment of the invention, during a write operation, a current which flows through the field effect transistor flows through the voltage path so that a voltage of the commonly connected sources is higher than a potential of the semiconductor base.
Thus, the invention described herein makes possible the advantages of providing a method and a circuit for writing data to a non-volatile semiconductor memory device in which it is possible to realize a high-speed write operation and a small layout area.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.